Compared to a digital phase locked loop (PLL), an analog PLL has the advantages of lower power consumption (e.g., approximately four times lower power consumption than a digital PLL), lower jitter (e.g., 3 to 5 times better than digital PLL), and lower cost in design, which are desired by low power devices such as server, client machines, system-on-chip (SOC), and wearable computing devices. As the push for low power, low jitter, and low area PLL design continues in 10 nm process node and beyond, the leakage from various sources could become an issue in the applications where the reference clock frequency is low and the static phase error is required to be close to zero at all process corners and temperatures. One effect of these leakage currents on analog PLLs is the increase of static phase error and reference spur. For PLLs with low reference clock frequency (e.g., large multiplication factor N), where the leakage current accumulates longer time (e.g., for a duration of a reference clock period), the control voltage Vctl of a voltage controlled oscillator (VCO) can drift higher or lower depending on the leakage current direction.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.